The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down has also increased the complexity of processing and manufacturing ICs.
IC design becomes more challenging as IC technologies continually progress towards smaller features. For example, an IC device includes a sequence of patterned layers and un-patterned layers that combine to form one or more IC features. Misalignment between the various layers can cause performance issues and even potentially cause an IC device to fail due to, for example, a short caused by misaligned layers. Overlay (generally referring to layer-to-layer positioning) of the various layers is thus a factor to ensuring the IC device and/or IC features function properly, and in particular, function according to design requirements for the IC device and/or IC feature.
In addition, a process window refers to the range of focus and exposure settings that will still produce the desired features into the photo-resist layer. For example, the smaller process window results in design rules requiring a minimum spacing between the contact openings and device features (e.g., gate structures), which provides a smaller than desirable margin of contact/gate structure overlay. Further, if the minimum spacing between the contact openings and such device features varies, poor device performance results, such as contact/gate structure short and contact open issue.
Although existing overlay error metrology techniques and process window improvement method have been generally adequate for their intended purposes, they have not been entirely satisfactory in when it comes to quickly and accurately assessing overlay issues for advanced technology nodes.